FIG. 1 shows a block diagram of a system-on-chip (SoC) 100. An SoC can include different device types, such as various combinations of digital and/or analog transistors that have distinct performance requirements, and can include differing structures, voltages, and/or interconnect conditions for operation. SoCs are advantageous in that the on-chip integration of a multiplicity of functional blocks offer smaller size, improved performance, and lower power than systems that use multiple integrated circuits that are separately packaged and electrically connected together by motherboard, stack package, or through silicon via interconnects.
As seen in FIG. 1, a variety of different designs can exist on a single SoC 100. The SoC 100 may include conventional digital logic 104, analog 108, input 102 and output 106, SRAM 112 and 114, and possibly other functional blocks 110, each of which may be interconnected to each other within the die via a common bus, wire traces, or other suitable interconnections. The device types supporting each of the functional blocks and designs can differ, for example, in size, operating voltage, switching speed, threshold voltage, applied body bias, source and drain dopant implants, gate stack dielectric materials, gate metals, or digital or analog operation. The devices are preferably formed or otherwise processed as bulk complementary metal-oxide-semiconductor (CMOS) on a common substrate (as opposed to silicon-on-insulator), typically silicon or other similar substrate. SoCs are often used in computing devices, embedded control systems, integrated wireless controllers, cell phones, network routers or wireless points, sensors, mechanical or electrical controllers, or the like.
An SoC 100 can have various performance requirements. For example, it is desirable for an SoC 100 to operate at high speeds. At the same time, it is desirable for an SoC 100 to be power efficient. Lowering a power supply voltage of an SoC 100 can be an effective way to reduce both switching and leakage power in very large scale integration (VLSI) circuits of an SoC 100. However, at the device level, it can be necessary to reduce the threshold voltage of transistors in conjunction with lowering the power supply voltage in order to satisfy target speed requirements of the SoC. The resulting reduction of threshold voltages can contribute to an exponential increase of sub-threshold leakage currents for the SoC. Thus, increased leakage power can become a significant factor for the SoC as the technology is being scaled.
In addition, on-chip process variations in advanced technologies can cause large variations in threshold voltages of transistors thereby further degrading the performance of SoCs.